1. Field of the Invention
Embodiments of the invention relate to the field of computer system management, and more specifically, to system management interrupts.
2. Description of Related Art
On many computer platforms, system management interrupt (SMI) is a global event that causes all the logical processors in the system to be brought into the system management mode (SMM). Usually, the SMI is a front-side bus (FSB) pin that is asserted to signal the SMI event. In a typical scenario, one of the logical processors processes SMI while other processors wait within the SMM code for an exit signal from this processor. Such a rendezvous logic ensures that while the SMI is being handled, no other processors may make conflicting accesses to the platform resources being manipulated by the SMM code.
While the current SMI design may offer a solution for avoiding resource conflicts, it suffers a number of disadvantages. First, it may waste processing time. In many SMI instances, other processors are forced to enter the SMM and stay idle. Therefore, considerable time quantum is wasted in synchronizing actions of multiple processors in the system. Second, future interconnects may not have a physical SMI pin. Accordingly, transitions of multiple processors into the SMM may not occur simultaneously. Third, there may be significant overheads associated with polling multiple status registers spread across several components in the system. Fourth, SMI handling may be inefficient in event handler invocation or due to the sequential execution of the SMI code in a multiprocessing environment, especially when multiple sources assert the SMI concurrently.